Local oxidation of silicon (LOCOS) has become a popular method of fabricating semiconductor devices. LOCOS typically involves forming isolating dielectric regions between active regions of devices, to electrically isolate each device sharing a common substrate. These isolating dielectric regions are typically formed by thermally growing oxide between stacks of nitride on silicon oxide disposed over areas that will become active regions of the substrate. Using conventional LOCOS techniques, the thermally grown isolating oxide generally tends to encroach into the active regions of the substrate, limiting the packing density of semiconductor devices in the resulting structure.
One approach to reducing the encroachment of the isolation dielectric into the active regions of the substrate is to form a thick nitride shield over a pad oxide, which is disposed on the substrate. A problem with this approach, however, is that the presence of the thick nitride shield stresses the silicon in the active region during formation of the isolation dielectric which creates stress related imperfections, such as dislocations, in the silicon. An additional problem with this approach is that the resulting structure exhibits a non-planar surface, which makes focusing lithography equipment difficult.
Another approach to protecting the substrate from these stresses is commonly referred to as poly-buffered LOCOS (PBL). This approach involves forming a disposable polysilicon buffer layer between the pad oxide and the nitride shield to absorb stresses from the nitride on the substrate. Although the polysilicon buffer layer acts to absorb some stress, this approach still suffers from difficulties in lithography created by the resultant nonplanar surfaces. Still another approach, referred to as sidewall-sealed poly-buffered LOCOS (SSPBL) is similar to PBL, with the added features of etching a trench into the silicon and implementing sidewall protective structures in an effort to limit encroachment of the isolation oxide and maintain a planar surface. Each of these approaches has a disadvantage of using a disposable polysilicon buffer structure, which must later be replaced with another silicon structure to form a gate, resulting in additional fabrication time and expense.